The MIT SCALE project

Thursday, November 21, 2002 - 7:00pm
AI Lab, 8th fl
Krste Asanovic

Joint GBC/ACM IEEE Computer Society meeting

The SCALE (Software-Controlled Architectures for Low Energy) project is developing a new all purpose computing architecture for future embedded and general-purpose systems. For many applications, power consumption will be the primary constraint on system performance, cost, and size. A major emphasis in the SCALE project is the development of new techniques that give software fine-grain control over processor energy usage. By exposing hardware energy consumption to software, we can exploit compile-time knowledge to reduce run-time energy dissipation. This talk will provide an overview of the current state of the SCALE project and present early results on energy-exposed instruction sets.

Lecturer Biography: 

Krste Asanovic joined MIT in 1998 as an assistant professor in the Department of Electrical Engineering and Computer Science and is a member of the MIT Laboratory for Computer Science. At MIT, he leads the SCALE project, which is investigating new energy-efficient microprocessor designs. Prof. Asanovic received a bachelor's degree in Electrical and Information sciences from Cambridge University in 1987 and a doctorate in Computer Science from the University of California, Berkeley, in 1998. From 1987-89 he was at the GEC Hirst Research Center in London where he co-architected the SPACE associative processor containing over 170,000 SIMD processors. At Berkeley, he led the development of the T0 vector microprocessor and was an early contributor to the Berkeley IRAM project. He is currently serving as a member of the technical program committees for the International Solid-State Circuits Conference and the International Symposium on Computer Architecture. He is also serving as a DARPA ISAT member.